Prior art data transfer systems, such as the system 100 in FIG. 1, often contain a pre-charging transistor 102 coupled to the data bus 104 for precharging the bus 104 to a logic high level (e.g., 5 volts). This approach normally assumes that it is faster to pull the bus voltage down to a logic low level (e.g., 0 volts) from the logic high level, than the reverse. The pull-down transistors 106, 110 and 114 with their respective bus logic 108, 112 and 116 are operated to pull the bus voltage down to the logic low level by creating conduction paths to ground when activated.
The bus 104 is maintained at a logic high voltage, which voltage is nearly instantaneously available at an input of an inverter 118. The bus 104 is pulled down when a logic low voltage is to be provided to the inverter 118. Pre-charging can thus increase the operating speed of data transfer systems.
However, repeated pre-charging cycles without the intervention of a pull-down operation can raise the pre-charge voltage to such a high level that the overall advantage of pre-charging is lost since the time for going from the logic high voltage to the logic low voltage is directly proportional to the precharge voltage.
U.S. patent application Ser. No. 284,644 entitled "High Speed Computer Data Transfer System" and assigned to the assignee of the present invention teaches the use of a clamping circuit to solve the above problems. That application is hereby expressly incorporated by reference. The present invention is directed to producing a more reliable data transfer system wherein body effect upon the pre-charging regulation components is reduced (thus for example, threshold voltages are more stable). Body effect is the effect upon semiconductor components caused by built-in voltages in the substrate layer.